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-- Company:        EECS 452
-- Engineer:       Kurt Metzger
-- 
-- Create Date:    12:14:52 04/13/2008 
-- Design Name: 
-- Module Name:    DisplayManager - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DisplayManager is
    Port ( Haddr : in  STD_LOGIC_VECTOR (9 downto 0);
           Vaddr : in  STD_LOGIC_VECTOR (9 downto 0);
           red : out  STD_LOGIC_VECTOR (2 downto 0);
           grn : out  STD_LOGIC_VECTOR (2 downto 0);
           blu : out  STD_LOGIC_VECTOR (2 downto 1);
           req_out : out STD_LOGIC;
           ack_in  : in STD_LOGIC;
           active : in STD_LOGIC;
           display_address : out  STD_LOGIC_VECTOR (17 downto 0);
           data_in : in  STD_LOGIC_VECTOR (31 downto 0); -- 4 pixels
           clk : in  STD_LOGIC);
end DisplayManager;

architecture Behavioral of DisplayManager is

   signal pixel_addr : std_logic_vector (18 downto 0);
   signal pixel_quad : std_logic_vector (31 downto 0);
   signal pixel : std_logic_vector (7 downto 0);
   signal addr_sr : std_logic_vector (1 downto 0);
 
begin

   pixel_addr <= ("000000000" & Haddr) + (Vaddr & "000000000") + ("00" & Vaddr & "0000000");
   display_address <= pixel_addr(18 downto 1);
         
   red <= (pixel(7) and active) & (pixel(6) and active) & (pixel(5) and active);
   grn <= (pixel(4) and active) & (pixel(3) and active) & (pixel(2) and active);
   blu <= (pixel(1) and active) & (pixel(0) and active);
   
   with pixel_addr(1 downto 0) select
      pixel <= pixel_quad(31 downto 24) when "00", 
               pixel_quad(23 downto 16) when "01",
               pixel_quad(15 downto  8) when "10",
               pixel_quad( 7 downto  0) when others;
   	
   display : process(clk)
   begin
      if rising_edge(clk) then
         addr_sr <= addr_sr(0) & pixel_addr(0);
         if (addr_sr = "01") and (pixel_addr(1) = '1') then
            pixel_quad <= data_in;
            req_out <= '1';
         end if;
         if ack_in = '1' then
            req_out <= '0';
         end if;
      end if;
   end process;

end Behavioral;

